Background
The increasing power demand of artificial intelligence (AI) andhigh-performance computing (HPC) systems is driving the adoption of IntegratedVoltage Regulators (IVRs) embedded directly within package substrates. Byplacing power conversion closer to the processor, IVRs improve power deliveryefficiency and reduce electrical losses. However, the heat generated by theseregulators introduces additional thermal loads within the package, potentiallyincreasing GPU junction temperatures and reducing overall system performance.
As future AI accelerators move towards multi-kilowatt power levels,understanding and mitigating the thermal impact of embedded IVRs is becoming acritical design challenge. Emerging package architectures are exploringdouble-sided cooling and alternative heat extraction paths through the packagebackside, but their effectiveness and design trade-offs remain insufficientlyunderstood.
Objective
The objective of this thesis is to investigate the thermal couplingbetween embedded IVRs and GPUs and develop thermal mitigation strategies fornext-generation AI and HPC packages through advanced thermal modelling andsimulation.
Research Scope
The student will develop detailed thermal models of advanced GPUpackages containing embedded IVRs and evaluate the influence of IVR powerdissipation on package and GPU temperatures. The work will focus on:
Methodology
The research will primarily rely on finite-element simulations usingstate-of-the-art modeling tools. Thermal resistance breakdowns, temperaturedistributions, and heat-flow analyses will be used to evaluate various packagearchitectures and cooling concepts. Design trade-offs between thermalperformance, package complexity, and implementation feasibility will beassessed.
Expected Outcomes
The thesis will deliver:
Candidate Profile
The project is suitable for Master students in Mechanical Engineering,Applied Physics or Electromechanical Engineering with an interest in thermalmanagement, semiconductor packaging, and numerical simulation. Thermalmodelling or finite element theory experience is required.
Type of internship: Master internship
Duration: 1 year
Required educational background: Mechanical Engineering, Electromechanical engineering
University promotor: Houman Zahedmanesh (KU Leuven)
Supervising scientist(s): For further information or for application, please contact Onur Yenigun (< E-Mail aus Sicherheitsgründen gelöscht >)
The reference code for this position is 2026-INT-304. Mention this reference code in your application.
Only for self-supporting students.
Applications should include the following information:
Incomplete applications will not be considered.
The increasing power demand of artificial intelligence (AI) andhigh-performance computing (HPC) systems is driving the adoption of IntegratedVoltage Regulators (IVRs) embedded directly within package substrates. Byplacing power conversion closer to the processor, IVRs improve power deliveryefficiency and reduce electrical losses. However, the heat generated by theseregulators introduces additional thermal loads within the package, potentiallyincreasing GPU junction temperatures and reducing overall system performance.
As future AI accelerators move towards multi-kilowatt power levels,understanding and mitigating the thermal impact of embedded IVRs is becoming acritical design challenge. Emerging package architectures are exploringdouble-sided cooling and alternative heat extraction paths through the packagebackside, but their effectiveness and design trade-offs remain insufficientlyunderstood.
Objective
The objective of this thesis is to investigate the thermal couplingbetween embedded IVRs and GPUs and develop thermal mitigation strategies fornext-generation AI and HPC packages through advanced thermal modelling andsimulation.
Research Scope
The student will develop detailed thermal models of advanced GPUpackages containing embedded IVRs and evaluate the influence of IVR powerdissipation on package and GPU temperatures. The work will focus on:
- Quantifying the thermal impact of embedded IVRs on GPU hotspot and junction temperatures.
- Understanding heat flow paths and thermal coupling mechanisms between IVRs and compute dies.
- Investigating the effectiveness of double-sided cooling architectures.
- Exploring alternative heat extraction paths toward the package backside through thermal vias, heat spreaders, and high-conductivity materials.
- Performing parametric studies on IVR location, substrate properties, package stack-up, and cooling configurations.
- Generating design guidelines for thermally optimized integration of power delivery in advanced packages.
Methodology
The research will primarily rely on finite-element simulations usingstate-of-the-art modeling tools. Thermal resistance breakdowns, temperaturedistributions, and heat-flow analyses will be used to evaluate various packagearchitectures and cooling concepts. Design trade-offs between thermalperformance, package complexity, and implementation feasibility will beassessed.
Expected Outcomes
The thesis will deliver:
- Thermal modelling framework for GPU packages with embedded IVRs.
- Quantitative assessment of the thermal penalty introduced by embedded power delivery.
- Comparative evaluation of single-sided and double-sided cooling approaches.
- Identification of critical thermal pathways and bottlenecks.
- Design recommendations for future AI and HPC package architectures incorporating embedded voltage regulation.
Candidate Profile
The project is suitable for Master students in Mechanical Engineering,Applied Physics or Electromechanical Engineering with an interest in thermalmanagement, semiconductor packaging, and numerical simulation. Thermalmodelling or finite element theory experience is required.
Type of internship: Master internship
Duration: 1 year
Required educational background: Mechanical Engineering, Electromechanical engineering
University promotor: Houman Zahedmanesh (KU Leuven)
Supervising scientist(s): For further information or for application, please contact Onur Yenigun (< E-Mail aus Sicherheitsgründen gelöscht >)
The reference code for this position is 2026-INT-304. Mention this reference code in your application.
Only for self-supporting students.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.
