Join imec, one of the world's premier research centers in nanotechnology, at its headquarters in Leuven, Belgium, to study the reliability of the most advanced 3D technology: wafer to wafer hybrid-bonding. Understanding the reliability of the SiCN wafer-to-wafer interface is key in assessing the reliability of this technology.
As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106 mm−2.
Wafer to wafer hybrid bonding connects two fully processed wafers with compatible die sizes through copper pads and a bonding dielectric, which, at imec, is SiCN (shown in Fig. 1). Unfortunately, this novel technology comes along with key reliability challenges. The constant pitch down-scaling results in an increased leakage current along the bonding interface which can be further enhanced by pad-to-pad misalignment. While this misalignment can be mitigated with imec unequal pad schemes, the resulting copper-dielectric interface could lead to metal ion drift at elevated temperature and electric fields.
The study aims to characterize the intrinsic reliability of various SiCN dielectric materials as potential candidates for the bonding interface. A special emphasis will be placed on understanding the impact of the dielectric composition on the defect generation rate and on the nature of the defects.
The following activities are foreseen:
Type of internship: Master internship
Duration: 4-6 months
Required educational background: Materials Engineering, Physics
Supervising scientist(s): For further information or for application, please contact Emmanuel Chery (< E-Mail aus Sicherheitsgründen gelöscht >)
The reference code for this position is 2026-INT-274. Mention this reference code in your application.
Only for self-supporting students.
Applications should include the following information:
Incomplete applications will not be considered.
As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106 mm−2.
Wafer to wafer hybrid bonding connects two fully processed wafers with compatible die sizes through copper pads and a bonding dielectric, which, at imec, is SiCN (shown in Fig. 1). Unfortunately, this novel technology comes along with key reliability challenges. The constant pitch down-scaling results in an increased leakage current along the bonding interface which can be further enhanced by pad-to-pad misalignment. While this misalignment can be mitigated with imec unequal pad schemes, the resulting copper-dielectric interface could lead to metal ion drift at elevated temperature and electric fields.
The study aims to characterize the intrinsic reliability of various SiCN dielectric materials as potential candidates for the bonding interface. A special emphasis will be placed on understanding the impact of the dielectric composition on the defect generation rate and on the nature of the defects.
The following activities are foreseen:
- SiCN reliability data will be collected using various methodologies (constant voltage/current stresses, interrupted/uninterrupted stress) at high and low temperatures to trigger dielectric degradation.
- Data preparation and data analyses will be performed by the student.
- Finally, a lifetime model will be developed to estimate the maximum use voltage and temperature for various mission profiles.
Type of internship: Master internship
Duration: 4-6 months
Required educational background: Materials Engineering, Physics
Supervising scientist(s): For further information or for application, please contact Emmanuel Chery (< E-Mail aus Sicherheitsgründen gelöscht >)
The reference code for this position is 2026-INT-274. Mention this reference code in your application.
Only for self-supporting students.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.
