CMOS2.0 challenges design-technology co-optimization research to look beyond pinpointing a complex device architecture with an optimal power, performance, and area (PPA) trade-off. Pathfinding research in the CMOS2.0 era requires not only meticulously tailoring trade-offs towards the envisioned application, but also diversifying trade-offs within one application. As different subcircuits within one application, e.g., a CPU, could benefit different trade-offs, enabling significant differences in technology within on application, addressing these trade-offs for subcircuits individually is key for pathfinding research.
In this PhD, you will assess both existing and innovative device and technology options, physical design space, and integration for these subcircuits from a pathfinding, forward looking perspective.
You will develop cell level models for various technology options, leveraging and expanding on imec's existing DTCO modeling framework. The active part of the device will be modeled through TCAD simulations, and a compact model (CM) fitted to the subsequent TCAD data, whereas the Mid-Of-Line (MOL) parasitics will be modeled through parasitic extraction (PEX) using a full-field 3D solver. You will use these cell level models to benchmark different device and technology options for multifarious design points. Based on your assessments, you will optimize a set of devices and technologies progressing towards the CMOS2.0 era.
Required background: Nanotechnology, Electrical Engineering or equivalent.
Type of work: 75% modeling/simulation/design, 25% literature
Supervisor: (to be defined/not in list)
Co-supervisor: (to be defined/not in list)
Daily advisor: Sheng Yang, Hannah Watson
The reference code for this position is 2026-217.
In this PhD, you will assess both existing and innovative device and technology options, physical design space, and integration for these subcircuits from a pathfinding, forward looking perspective.
You will develop cell level models for various technology options, leveraging and expanding on imec's existing DTCO modeling framework. The active part of the device will be modeled through TCAD simulations, and a compact model (CM) fitted to the subsequent TCAD data, whereas the Mid-Of-Line (MOL) parasitics will be modeled through parasitic extraction (PEX) using a full-field 3D solver. You will use these cell level models to benchmark different device and technology options for multifarious design points. Based on your assessments, you will optimize a set of devices and technologies progressing towards the CMOS2.0 era.
Required background: Nanotechnology, Electrical Engineering or equivalent.
Type of work: 75% modeling/simulation/design, 25% literature
Supervisor: (to be defined/not in list)
Co-supervisor: (to be defined/not in list)
Daily advisor: Sheng Yang, Hannah Watson
The reference code for this position is 2026-217.
