The rapid growth of AI-driven applications today is pushing conventional charge-based memory technologies to their limits due to the concerns in reliability, scalability, and volatility. This pushes a pressing need for alternative memory solutions that offer faster operation, higher endurance, and non-volatile data storage.
Spintronics, which exploits electron spin in addition to charge, offers a promising pathway for next-generation memory. Its combination of non-volatility, fast switching, and high integration density makes Magnetic Random-Access Memory (MRAM) a strong candidate to complement or replace conventional charge-based memories across the memory hierarchy.
MRAM uses Magnetic Tunnel Junctions (MTJs) to store and read information through the magnetic state and Tunnelling Magnetoresistance (TMR). While STT-MRAM suffers from high switching currents and reliability concerns, SOT-MRAM separates read and write paths for faster switching and improved endurance. However, switching the entire magnetic layer remains energy-intensive, and reliable field-free switching is still a major challenge.
Single-bit domain-wall (DW) devices offer an attractive alternative by encoding information in the position of a DW within an extended magnetic layer. Since only the DW needs to be displaced rather than the entire magnetic layer reversed, switching energy can be significantly reduced. DW devices can also operate without an external magnetic field, making them promise scalable and energy-efficient memory.
At imec, we have demonstrated full electrical control of nanoscale DWs using MTJs on 300 mm wafer for both writing and reading, providing an important proof-of-concept for practical DW manipulation at the nanoscale [1]. Building on this work, the project will investigate the physics of DW motion, with a particular focus on reliable DW confinement near the MTJ. A key challenge is to control the position of DW while maintaining low-power operation. Because DWs can move easily under a small driving current, excessive driving may cause DW to move beyond the intended storage region, leading to loss of information. This project will investigate different strategies to reliably confine the DW while maintaining low-power operation and compatibility with CMOS-scalable devices.
This project explores geometrical pinning strategies to prevent DW annihilation and achieve reliable DW confinement. The study will investigate the influence of geometrical design on DW dynamics under both magnetic field- and SOT-driven DW motion. Different pinning geometries will be designed and systematically investigated using micromagnetic simulations with OOMMF and MuMax. The simulations will provide insight into the underlying DW dynamics and the effectiveness of different confinement schemes, guiding the development of robust and low-power DW-based memory devices. The results will provide practical design guidelines for optimizing geometrical pinning in future 1-bit DW-MRAM devices.
https://www.imec-int.com/en/articles/imec-brings-magnetic-domain-wall-devices-closer-industrial-reality
Type of internship: PhD internship, Master internship
Duration: 6 months to one year
Required educational background: Materials Engineering, Physics, Nanoscience & Nanotechnology
Supervising scientist(s): For further information or for application, please contact Van Dai Nguyen (< email supprimé pour raison de sécurité >)
The reference code for this position is 2026-INT-350. Mention this reference code in your application.
Only for self-supporting students.
Applications should include the following information:
Incomplete applications will not be considered.
Spintronics, which exploits electron spin in addition to charge, offers a promising pathway for next-generation memory. Its combination of non-volatility, fast switching, and high integration density makes Magnetic Random-Access Memory (MRAM) a strong candidate to complement or replace conventional charge-based memories across the memory hierarchy.
MRAM uses Magnetic Tunnel Junctions (MTJs) to store and read information through the magnetic state and Tunnelling Magnetoresistance (TMR). While STT-MRAM suffers from high switching currents and reliability concerns, SOT-MRAM separates read and write paths for faster switching and improved endurance. However, switching the entire magnetic layer remains energy-intensive, and reliable field-free switching is still a major challenge.
Single-bit domain-wall (DW) devices offer an attractive alternative by encoding information in the position of a DW within an extended magnetic layer. Since only the DW needs to be displaced rather than the entire magnetic layer reversed, switching energy can be significantly reduced. DW devices can also operate without an external magnetic field, making them promise scalable and energy-efficient memory.
At imec, we have demonstrated full electrical control of nanoscale DWs using MTJs on 300 mm wafer for both writing and reading, providing an important proof-of-concept for practical DW manipulation at the nanoscale [1]. Building on this work, the project will investigate the physics of DW motion, with a particular focus on reliable DW confinement near the MTJ. A key challenge is to control the position of DW while maintaining low-power operation. Because DWs can move easily under a small driving current, excessive driving may cause DW to move beyond the intended storage region, leading to loss of information. This project will investigate different strategies to reliably confine the DW while maintaining low-power operation and compatibility with CMOS-scalable devices.
This project explores geometrical pinning strategies to prevent DW annihilation and achieve reliable DW confinement. The study will investigate the influence of geometrical design on DW dynamics under both magnetic field- and SOT-driven DW motion. Different pinning geometries will be designed and systematically investigated using micromagnetic simulations with OOMMF and MuMax. The simulations will provide insight into the underlying DW dynamics and the effectiveness of different confinement schemes, guiding the development of robust and low-power DW-based memory devices. The results will provide practical design guidelines for optimizing geometrical pinning in future 1-bit DW-MRAM devices.
https://www.imec-int.com/en/articles/imec-brings-magnetic-domain-wall-devices-closer-industrial-reality
Type of internship: PhD internship, Master internship
Duration: 6 months to one year
Required educational background: Materials Engineering, Physics, Nanoscience & Nanotechnology
Supervising scientist(s): For further information or for application, please contact Van Dai Nguyen (< email supprimé pour raison de sécurité >)
The reference code for this position is 2026-INT-350. Mention this reference code in your application.
Only for self-supporting students.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.
