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[NanoIC topic] Investigation of write reliability in spin orbit torque-driven MRAM

Stage 25 à 36 mois

Leuven (Belgium)

Publiée le 2 septembre 2026

  • Contrat

    Stage 25 à 36 mois

  • Lieu

    Leuven (Belgium)

  • Date de début

    Dès que possible

  • Salaire

    Information non renseignée

  • Télétravail

    Non spécifié

Therapid growth of AI-driven applications today is pushing conventionalcharge-based memory technologies to their limits due to the concerns inreliability, scalability, and volatility. This pushes a pressing need foralternative memory solutions that offer faster operation, higher endurance, andnon-volatile data storage.

Spintronics,which leverages the electron's spin in addition to its charge, offers apromising pathway for next-generation memory technologies. MagneticRandom-Access Memory (MRAM) combines these advantages, offering high enduranceand fast read/write speeds, making it a strong candidate for future memorytechnologies. Spin-Orbit Torque MRAM (SOT-MRAM) is one of the most promisingMRAM concepts with demonstrated reliability of its constituent magnetic tunneljunction (MTJ) devices up to 1015 - 1018 cycles forultra-low write latencies down to 200 ps, thereby making it an attractiveproposition for future AI-ready compute and high performance systems [1].

To advance SOT-MRAM toward practical applications, itis essential to enable deterministic write schemes, low power read/writeoperations, high endurance and application-relevant data retention metrics. Thebenefits of reliable magnetization switching at low currents are multi-fold, asit directly improves energy efficiency, device reliability, and endurance. Toensure reasonable data retention, the MTJ stacks are engineered to have strongperpendicular magnetic anisotropy, thus enabling reliable data storage withgood data integrity. However, the switching current is typically inverselyrelated to retention in conventional MRAM technology, creating a fundamentaltrade-off. Therefore, understanding the relationship between switching currentand magnetic anisotropy and thermal stability is crucial for designingenergy-efficient, nanoscale SOT-MRAM devices and guiding future materialdevelopment.

The aimof this internship is to investigate the impact of material systems and devicedesign engineering on the switching/write reliability and its correlation withthe thermal stability (= data retention) of SOT-MRAM cells using advancedelectrical characterization techniques. This work will focus on elucidating therelationship between switching current and retention and, if time permits, itsevolution at reduced device dimensions. By studying the underlying switchingmechanisms through advanced electrical and physical characterization, thisinternship will contribute to enabling reliable switching in nanoscale SOT-MRAMand advancing scalable, energy-efficient memory technologies.

We seek a candidate with a physics orengineering background, a strong interest in experimental work, and a passionfor cutting-edge science and technology, particularly in the fast-growing areaof memory technology.

References:
https://www.nature.com/articles/s44306-024-00044-1

Type of internship: Master internship

Duration: 6 - 9 months

Required educational background: Electrotechnics/Electrical Engineering, Materials Engineering, Nanoscience & Nanotechnology, Physics

University promotor: Kristiaan Temst (KU Leuven)

Supervising scientist(s): For further information or for application, please contact Siddharth Rao (< email supprimé pour raison de sécurité >) and Van Dai Nguyen (< email supprimé pour raison de sécurité >)

The reference code for this position is 2026-INT-105. Mention this reference code in your application.

Only for self-supporting students.

Applications should include the following information:
  • resume
  • motivation
  • current study

Incomplete applications will not be considered.

Date limite de candidature

Tant que l’offre est en ligne

Niveau d'étude

Niveau Master, MSc ou Programme Grande Ecole

Fonction

Technologie

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