Modern computing platforms increasingly rely on specialized accelerators to meet the performance and energy demands of artificial intelligence and data-intensive applications. While accelerator architectures continue to improve computational efficiency, overall system performance and power consumption are often determined by the behavior of the memory subsystem. Memory access patterns generated by accelerator workloads can significantly influence DRAM latency, bandwidth utilization, energy consumption, and thermal characteristics. As a result, understanding the interaction between accelerators and memory systems has become essential for architecture exploration and design optimization.
This internship aims to study memory behavior under realistic AI workloads. Integrating a DRAM simulator with an AI accelerator in a chiplet system, the work enables end-to-end analysis of accelerator-generated memory traffic and its impact on DRAM performance, command activity, power consumption, and thermal behavior. Beyond establishing the integration itself, the internship will investigate how workload characteristics, memory configurations, and DRAM technologies influence system efficiency, providing a foundation for future research on memory-aware accelerator and chiplet-based system design.
Type of internship: Master internship
Duration: 4 months
Required educational background: Electrotechnics/Electrical Engineering, Computer Science
Supervising scientist(s): For further information or for application, please contact Katayoon Basharkhah (< email supprimé pour raison de sécurité >)
The reference code for this position is 2026-INT-294. Mention this reference code in your application.
Imec allowance will be provided.
Applications should include the following information:
Incomplete applications will not be considered.
This internship aims to study memory behavior under realistic AI workloads. Integrating a DRAM simulator with an AI accelerator in a chiplet system, the work enables end-to-end analysis of accelerator-generated memory traffic and its impact on DRAM performance, command activity, power consumption, and thermal behavior. Beyond establishing the integration itself, the internship will investigate how workload characteristics, memory configurations, and DRAM technologies influence system efficiency, providing a foundation for future research on memory-aware accelerator and chiplet-based system design.
Type of internship: Master internship
Duration: 4 months
Required educational background: Electrotechnics/Electrical Engineering, Computer Science
Supervising scientist(s): For further information or for application, please contact Katayoon Basharkhah (< email supprimé pour raison de sécurité >)
The reference code for this position is 2026-INT-294. Mention this reference code in your application.
Imec allowance will be provided.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.
