Context
Advanced HBM-GPUintegration is a key enabler for next-generation AI systems, yet thermalconstraints remain a primary limiter. imec has recently demonstratedsystem-technology co-optimization approaches to mitigate thermal bottlenecks inadvanced HBM-GPU concepts under realistic power conditions.
However,early-stage design decisions are still often dominated by expensive, slowiteration cycles. There is a strong need for fast, data-driven screeningmethodologies that can translate power dissipation signatures into actionableguidance on which integration solutions should be prioritized for detailedanalysis.
Objective
Develop a portablemethodology and prototype toolchain that leverages power-map analytics toenable early-stage screening and prioritization of candidate advancedintegration solutions. The internship focuses on building robust,architecture-consistent power-map descriptors and a scoring workflow thatsupports design-space exploration under limited information.
Keyresponsibilities
Power-mapprocessing pipeline (Python-first)
Builda reproducible pipeline to ingest, normalize, re-bin, and analyzeworkload-derived power maps; support multiple map formats and resolutions.
Featureengineering for power-map "fingerprints"
Defineand implement multi-scale spatial descriptors capturing power concentration,heterogeneity, clustering behavior, and structural regularities in a way thatis robust across workloads and mapping conventions.
Architecture-consistentsynthetic power-map generation
Createsynthetic power-map variants that remain consistent with computer-architecturerealities (e.g., clustered activity, compute/memory locality, floorplanconstraints), to stress-test methodology robustness and generalization.
Screeningscore and decision workflow
Proposea scoring framework that can rank candidate integration solutions usingpower-map fingerprints and limited configuration metadata, with emphasis onstability, interpretability, and sensitivity analysis.
Validationand reporting
Validatethe screening workflow against a small set of reference cases and produce aconcise report summarizing methodology, robustness, and recommended usageboundaries.
Optionalstretch goal
Exploregenerative data augmentation (e.g., GAN-style synthesis) to enrich the space ofarchitecture-consistent power maps for robustness testing (kept optional andscoped to feasibility).
Candidateprofile
MScor early PhD student in Electrical/Computer Engineering, Computer Architecture,or related fields.
Stronghands-on programming skills; Python required (NumPy/Pandas; bonus:SciPy/scikit-learn).
Solidunderstanding of computer architecture and workload behavior (powerdistribution drivers, compute/memory interaction).
Comfortablewith building end-to-end research prototypes: data processing, metrics design,benchmarking, and clear documentation.
Interestin thermal/power topics and advanced packaging is a plus, but the internship isprimarily methodology- and tooling-driven.
Whatyou will deliver
Aclean and reproducible Python toolchain for power-map analytics and screening.
Adocumented set of power-map fingerprints and a screening score.
Ashort technical report including robustness analysis and recommended bestpractices for using the methodology in early-stage exploration.
Reference:
https://www.imec-int.com/en/press/imec-mitigates-thermal-bottleneck-3d-hbm-gpu-architectures-using-system-technology-co
https://www.imec-int.com/en/expertise/cmos-advanced-and-beyond/xtco
Chen, Y., Lofrano, M., Moolchandani, D., Oprins, H., Van Der Plas, G., Ryckaert, J., Biswas, D. and Myers, J., 2025, December. Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization. In 2025 IEEE International Electron Devices Meeting (IEDM) (pp. 1-4). IEEE.
https://ieeexplore.ieee.org/abstract/document/11353711
Environment:
Youwill work in imec's highly interdisciplinary research environment, at theintersection of system technology co-optimization (STCO), power and thermalmodeling, memory and architecture research, and EDA methodology development.
Theinternship is embedded in imec's XTCO program thermal pillar, where architectural, physical,and system-level considerations are jointly explored to address next-generationcompute challenges.
Youwill collaborate closely with researchers across power/thermal modeling, memoryintegration, system architecture, and EDA tooling, and gain exposure torealistic industrial design constraints, data, and workflows. The work ishands-on and methodology-driven, with a strong emphasis on building reusableanalysis pipelines rather than isolated simulations.
Dailyadvisors:
YukaiChen, Matthew Walker
Type of internship: Master internship, PhD internship
Duration: 6-12 Months
Required educational background: Electrotechnics/Electrical Engineering, Computer Science
Supervising scientist(s): For further information or for application, please contact Yukai Chen (< e-mail verwijderd om veiligheidsredenen >)
The reference code for this position is 2026-INT-140. Mention this reference code in your application.
Imec allowance will be provided.
Applications should include the following information:
Incomplete applications will not be considered.
Advanced HBM-GPUintegration is a key enabler for next-generation AI systems, yet thermalconstraints remain a primary limiter. imec has recently demonstratedsystem-technology co-optimization approaches to mitigate thermal bottlenecks inadvanced HBM-GPU concepts under realistic power conditions.
However,early-stage design decisions are still often dominated by expensive, slowiteration cycles. There is a strong need for fast, data-driven screeningmethodologies that can translate power dissipation signatures into actionableguidance on which integration solutions should be prioritized for detailedanalysis.
Objective
Develop a portablemethodology and prototype toolchain that leverages power-map analytics toenable early-stage screening and prioritization of candidate advancedintegration solutions. The internship focuses on building robust,architecture-consistent power-map descriptors and a scoring workflow thatsupports design-space exploration under limited information.
Keyresponsibilities
Power-mapprocessing pipeline (Python-first)
Builda reproducible pipeline to ingest, normalize, re-bin, and analyzeworkload-derived power maps; support multiple map formats and resolutions.
Featureengineering for power-map "fingerprints"
Defineand implement multi-scale spatial descriptors capturing power concentration,heterogeneity, clustering behavior, and structural regularities in a way thatis robust across workloads and mapping conventions.
Architecture-consistentsynthetic power-map generation
Createsynthetic power-map variants that remain consistent with computer-architecturerealities (e.g., clustered activity, compute/memory locality, floorplanconstraints), to stress-test methodology robustness and generalization.
Screeningscore and decision workflow
Proposea scoring framework that can rank candidate integration solutions usingpower-map fingerprints and limited configuration metadata, with emphasis onstability, interpretability, and sensitivity analysis.
Validationand reporting
Validatethe screening workflow against a small set of reference cases and produce aconcise report summarizing methodology, robustness, and recommended usageboundaries.
Optionalstretch goal
Exploregenerative data augmentation (e.g., GAN-style synthesis) to enrich the space ofarchitecture-consistent power maps for robustness testing (kept optional andscoped to feasibility).
Candidateprofile
MScor early PhD student in Electrical/Computer Engineering, Computer Architecture,or related fields.
Stronghands-on programming skills; Python required (NumPy/Pandas; bonus:SciPy/scikit-learn).
Solidunderstanding of computer architecture and workload behavior (powerdistribution drivers, compute/memory interaction).
Comfortablewith building end-to-end research prototypes: data processing, metrics design,benchmarking, and clear documentation.
Interestin thermal/power topics and advanced packaging is a plus, but the internship isprimarily methodology- and tooling-driven.
Whatyou will deliver
Aclean and reproducible Python toolchain for power-map analytics and screening.
Adocumented set of power-map fingerprints and a screening score.
Ashort technical report including robustness analysis and recommended bestpractices for using the methodology in early-stage exploration.
Reference:
https://www.imec-int.com/en/press/imec-mitigates-thermal-bottleneck-3d-hbm-gpu-architectures-using-system-technology-co
https://www.imec-int.com/en/expertise/cmos-advanced-and-beyond/xtco
Chen, Y., Lofrano, M., Moolchandani, D., Oprins, H., Van Der Plas, G., Ryckaert, J., Biswas, D. and Myers, J., 2025, December. Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization. In 2025 IEEE International Electron Devices Meeting (IEDM) (pp. 1-4). IEEE.
https://ieeexplore.ieee.org/abstract/document/11353711
Environment:
Youwill work in imec's highly interdisciplinary research environment, at theintersection of system technology co-optimization (STCO), power and thermalmodeling, memory and architecture research, and EDA methodology development.
Theinternship is embedded in imec's XTCO program thermal pillar, where architectural, physical,and system-level considerations are jointly explored to address next-generationcompute challenges.
Youwill collaborate closely with researchers across power/thermal modeling, memoryintegration, system architecture, and EDA tooling, and gain exposure torealistic industrial design constraints, data, and workflows. The work ishands-on and methodology-driven, with a strong emphasis on building reusableanalysis pipelines rather than isolated simulations.
Dailyadvisors:
YukaiChen, Matthew Walker
Type of internship: Master internship, PhD internship
Duration: 6-12 Months
Required educational background: Electrotechnics/Electrical Engineering, Computer Science
Supervising scientist(s): For further information or for application, please contact Yukai Chen (< e-mail verwijderd om veiligheidsredenen >)
The reference code for this position is 2026-INT-140. Mention this reference code in your application.
Imec allowance will be provided.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.
