Power semiconductor device manufacturingspans multiple material platforms, device architectures, voltage classes, waferformats, and integration schemes. The next step is to transform thesetechnology-specific models into a consistent generational framework thatenables like-for-like comparison while preservingthe process differences that define each platform.

Inthis internship, the student will build and extend a process-flow model forpower semiconductor manufacturing across different device generations andtechnologies. The student will:

Review and map existing process flows for selected power semiconductor devices and identify the key manufacturing steps and differences between technology generations.
Break down the process flows into reusable modules such as wafer preparation, epitaxy, isolation, implantation, thermal processing, metallization, passivation, and other relevant manufacturing steps.
Create generation-specific process-flow tables, defining parameters such as wafer size, material consumption, layer thickness, process conditions, number of process steps, and other relevant assumptions.
Collect and document the evidence behind process parameters and assumptions, and identify the main sources of uncertainty where data are not available.
Implement selected process-flow variants in the imec.netzero modelling environment and run environmental impact calculations.
Compare different technology generations to quantify how changes in device architecture and manufacturing processes affect cradle-to-gate environmental impact.
Summarize and visualize the results, identifying which process modules and technology changes are the main contributors to environmental impact and where further data or model refinement is needed.

Theoutcome will be a reusable process-flow modelling framework that can be extendedto additional power semiconductor generations and technologies, enablingsystematic comparison of their manufacturing-related environmental footprints.

Type of internship: PhD internship, Master internship

Duration: 1 year

Required educational background: Chemistry/Chemical Engineering, Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics

Supervising scientist(s): For further information or for application, please contact Joo Hyoung Kim (< email deleted for security reasons >)

The reference code for this position is 2026-INT-257. Mention this reference code in your application.

Imec allowance will be provided.

Applications should include the following information: